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1 of 21 112602 features rechargeable lithium-ion (li+) safety circuit - overvoltage protection - overcurrent/short-circuit protection - undervoltage protection - overtemperature protection controls high-side n-channel power mosfets driven from 9v charge pump system power management and control feature support eight bytes of lockable eeprom dallas 1-wire ? interface with unique 64-bit device address 8-pin sop package low power consumption: - active current: 12.5 a typ - sleep current: 1.5 a typ pin configuration pin description pls - battery-pack positive terminal input ps - power-switch sense input dq - data input/output v ss - device ground v dd - power-supply input cp - reservoir capacitor cc - charge control output dc - discharge control output description the DS2720 single-cell rechargeable li+ protection ic provides electronic safety functions required for rechargeable li+ applications including protecting th e battery during charge, protection of the circuit from damage during periods of excess current flow and maximization of battery life by limiting the level of cell depletion. protection is fa cilitated by electronically disconn ecting the charge and discharge conduction path with switching devices such as low-cost n-channel power mosfets. since the DS2720 provides high-side drive to extern al n-channel protection mosfets from a 9v charge pump, superior on-resistance performan ce results compared to common low-side protector circuits using the same fets. the fet on-resistance actually decreases as the battery discharges. adding to the uniqueness of the DS2720 is the ability of the system to control the fets from either the data interface or a dedicated input thereby eliminating the power-sw itch control redundancy of rechargeable li+ battery systems. through its 1-wire interface, the DS2720 gives the hos t system read/write access to status and control registers, instrumentation registers, and general-purpose data storage. each device has a factory- programmed 64-bit net address that allows it to be individually addresse d by the host system. DS2720u sop ps 3 2 1 45 6 7 8 pls dq v ss v dd cc dc cp DS2720 efficient, addressable single-cell rechargeable lith ium protection ic www.maxim-ic.com 1-wire is a registered trademark of dallas semiconductor.
DS2720 2 of 21 two types of user-memory are provided on the ds 2720 for battery information storage: eeprom and lockable eeprom. eeprom memory saves important batte ry data in true nonvolatile (nv) memory that is unaffected by severe ba ttery depletion, accidental shorts , or esd events. lockable eeprom becomes rom when locked to provide additi onal security for unchanging battery data. ordering information part description DS2720au DS2720 in 8-lead sop in bulk with v ova = 4.275v DS2720au/t&r DS2720 in 8-lead sop in tape-and-reel with v ova = 4.275v DS2720bu DS2720 in 8-lead sop in bulk with v ovb = 4.35v DS2720bu/t&r DS2720 in 8-lead sop in tape-and-reel with v ovb = 4.35v DS2720cu DS2720 in 8-lead sop in bulk with v ovc = 4.30v DS2720cu/t&r DS2720 in 8-lead sop in tape-and-reel with v ovc = 4.30v
DS2720 3 of 21 + + + + figure 1. block diagram 1) normally open, closed to enable test current, i tst 2) normally open, closed to enable test current, i tst , and recovery charge (see rechargeable li+ protection circuitry section for more information.) 64-bit rom 1-wire interface and control dq v dd v ov + + delay t ovd v ss v oc + + delay t uvd delay t scd delay t ocd lockable eeprom status/control temp sensor (tdevice) s r q v sc v ch + + pls output buffer cc dc cp v ce + + v uv s r q r tst l o g i c t max + + ps (1) (2)
DS2720 4 of 21 table 1. detailed pin description symbol description pls battery-pack positive terminal input. the device monitors the state of the battery pack?s positive terminal through this pin in order to detect events such as the attachment of a charger or the removal of a short circuit. connect pls to the pack positive terminal through a 100 resistor. ps power-switch sense input. the device wakes up from sleep mode when it senses the closure of a switch to v ss on this pin. ps has a high-impedance internal pullup. dq data input/out. 1-wire data line. open-drain output driver. connect this pin to the data terminal of the battery pack. dq has an internal 0.5 a pull-down. v ss device ground. connect directly to the negative terminal of the battery cell. v dd power supply input. connect v dd to the positive terminal of the battery cell through a decoupling network. cp charge pump output. the internal charge pump regulates cp to 9v which supplies the on state drive to the protection fets. connect a 0.1 f reservoir capacitor from cp to v ss . cc charge protection control output. controls an external n-channel high-side charge protection fet. dc discharge protection control output. controls an external n-channel high-side discharge protection fet. figure 2. application example cp cc dc ps pls vdd vss dq DS2720 1-cell li+ 1k 102 102 104 pack+ ps dat a pack- 100 330 330 10 104 102 1k
DS2720 5 of 21 power modes the DS2720 has two power modes: active and slee p. while in active mode, the DS2720 continuously performs safety monitoring. in sleep mode, the ds 2720 ceases monitoring activities and drives both the charge and discharge protection fets to an ?off stat e?. upon returning to the active mode from the sleep mode, DS2720 resumes safety monitoring and conditionally turns on the protection fets. table 2. power mode transition conditions active sleep sleep active (1) v dd < v uv ps pulled to v ss or v pls > v dd + v ch (1) DS2720 does not tr ansition to active mode if v dd < v sc . rechargeable li+ protection circuitry during active mode, the DS2720 constantly monitors cell voltage and voltage drop across the fets to protect the battery from overcharge (overvoltage), ove rdischarge (undervoltage), and excessive discharge currents (overcurrent, short circuit). conditions and DS2720 responses are described in the sections below and summarized in table 3 and figure 3. table 3. protection conditions and DS2720 responses activation condition name threshold delay response release threshold overvoltage v dd > v ov t ovd (1) cc = v olcc v dd < v ce or v dd - v pls > v oc undervoltage v sc < v dd < v uv t uvd cc = v olcc dc = v oldc v pls > v dd + v ch and v dd > v uv (charger connected) recovery charge v dd < v sc or (while in active mode) v dd < v ce r tst enabled (2) v dd v ce overcurrent v dd - v pls > v oc t ocd cc = v olcc dc = v olcc v pls > v dd - v oc (3) short circuit v dd < v sc t scd cc = v olcc dc = v oldc v pls > v dd - v oc (3) overtemperature t device > t max cc = v olcc dc = v oldc t device < t max all voltages are with respect to v ss . (1) during transition from sleep to active, t ovd = 0. (2) recovery charge current is limited by r tst and forward voltage of blocking diode, which prevents discharging through r tst when recovery charge enabled. (3) with test current i tst flowing from v dd to pls (pullup on pls).
DS2720 6 of 21 overvoltage. if the cell voltage sensed at v dd exceeds overvoltage threshold v ov for a period longer than overvoltage delay t ovd , the DS2720 shuts off the external char ge fet and sets the ov flag in the protection register. discharging remains enabled during overvoltage . the charge fet is re-enabled (unless another protection conditi on prevents it), when the cell voltage falls below charge enable threshold v ce , or a discharge causes v dd - v pls > v oc . undervoltage. if the cell voltage sensed at v dd drops below undervoltage threshold v uv for a period longer than undervoltage delay t uvd , the DS2720 shuts off the charge and discharge fets, sets the uv flag in the protection register, and enters sleep mode. the DS2720 turns on both the charge and discharge fets after the cell voltage rises above v uv and a charger is present. short circuit. if the cell voltage sensed at v dd drops below depletion threshold v sc for a period of t scd , the DS2720 shuts off the charge and discharge fets and sets the doc flag in the protection register. the current path through the charge and discharge fets is not re-established until the voltage on pls rises above v dd - v oc . the DS2720 provides a test current through internal resistor r tst from v dd to pls to pull up pls when v dd rises above v sc . the test current allows the ds 2720 to detect the removal of the offending low-impedance load. additionally, a recovery charge path through r tst from pls to v dd is enabled. overcurrent. if the voltage across the protection fets (v dd - v pls ) is greater than v oc for a period longer than t ocd , the DS2720 shuts off the external charge a nd discharge fets and sets the doc flag in the protection register. the current path is not re-established until the voltage on pls rises above v dd - v oc . the DS2720 provides a test current through internal resistor r tst from v dd to pls to detect the removal of the offending low-impedance load. overtemperature. if the device temperature exceeds t max , the DS2720 immediately shuts off the external discharge and charge fets. the fets are not turned back on until the cell temperature drops below t max and the host resets the ot bit.
DS2720 7 of 21 figure 3. li+ protection circuitry example waveforms notes: i oc = current that produces a voltage drop across fets equal to v oc threshold. i sc = current drawn from the battery during short-circuit event. (collapses the cell terminal voltage to v sc .) above example assumes fet on-resistance values such that the overcurrent threshold, v oc , is reached before the short-circuit threshold, v sc . power mode v ov v ce v uv v dd v pls - v dd cc dc -v oc 0 t sc d t ocd t u vd v ohcp v ohcp active v olcc v oldc sleep t ovd over- current or short test active inactive t uvd v sc i cell charge discharge -i sc -i oc 0 v ch t u vd t u vd recovery charged through enabled disabled recovery charge t on t on t on short-circuit event undervoltage event overvoltage event overcurrent event undervoltage event severe depletion
DS2720 8 of 21 memory the ds27xx family of products is organized into a 256-byte linear address space with registers for instrumentation, status, and control in the lower 32 bytes, with lockable eeprom memory occupying portions of the remaining address space. all eep rom memory is general purpose except address 31h, which should be written with the defau lt values for the status register. eeprom memory is shadowed by ram to eliminate programming delays between writes and to allow the data to be verified by the host system before being copied to eeprom. all reads and writes to/from eeprom memory in fact access the shadow ra m. in unlocked eeprom blocks, the write data command updates shadow ram. in locked eeprom bl ocks, the write data command is ignored. the copy data command copies the contents of shadow ram to eeprom in an unlocked block of eeprom but has no effect on locked blocks. the recall data command copies the contents of a block of eeprom to shadow ram regardless of whether the block is locked or not. table 4. memory map address (hex) description read/write 00 protection register r/w 01 status register r 02?06 reserved ? 07 eeprom register r 08 special feature register r/w 09?1f reserved ? 20?23 eeprom, block 0 r/w (1) 24?2f reserved ? 30?33 eeprom, block 1 (31 = status register initialization) r/w (1) 34?ff reserved ? (1) each eeprom block is read/write until locked by the lock command, after which it is read-only. protection register the protection register consists of flags that indi cate protection circuit stat us and switches that give conditional control over the charging and discharg ing paths. bits ov, uv, and doc are set when corresponding protection conditions o ccur and remain set until cleared by the host system. the format of the protection register is shown in figure 4. the functi on of each bit is described in detail in the following paragraphs. figure 4. protection register format address 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ov uv 0 doc cc dc ce de
DS2720 9 of 21 ov? overvoltage flag. when set to 1, this bit indicates the battery pack has experienced an overvoltage condition. this bit does not clear itself after the overvo ltage state is corrected, and thus must be reset by the host system. a reset of this bit should be issued after the battery voltage falls below v ce in order to detect future events. the ov bit is a volatile r/ w bit, initialized to 0 upon power-on-reset (por). uv ?undervoltage flag. when set to 1, this bit indicates the battery pack has experienced an undervoltage condition. this bit does not clear itself after the undervoltage state is corrected, and thus should be reset by the host system in order to det ect future events. the uv bit is a volatile r/w bit, initialized to 1 upon por. doc ?overcurrent flag. when set to 1, this bit indicates the battery pack has experienced an overcurrent (or short-circuit) cond ition. this bit does not clear itself af ter the over/shortcurrent state is corrected, and thus should be reset by the host system in order to detect future events. the doc bit is a volatile r/w bit, initialized to 1 upon por. cc ?cc pin mirror. this read-only bit mirrors the state of the cc output pin. the cc bit is a 1 when the cc pin is driven high (v ohcc ). the cc bit is a 0 when the cc pin is driven low (v olcc ). dc? dc pin mirror. this read-only bit mirrors the st ate of the dc output pin. the dc bit is a 1 when the dc pin is driven high (v ohdc ). the dc bit is a 0 when the dc pin is driven low (v oldc ). ce ?charge enable. writing a 0 to this bit disables charging (cc output low, external charge fet off) regardless of cell or pack conditions. writing a 1 to this bit enables charging, subject to override by the presence of any protection conditions. the DS2720 auto matically sets this bit to 1 when it transitions from sleep mode to active mode. the ce bit is a volatile r/w bit, initialized to 1 upon por. de ?discharge enable. writing a 0 to this bit disables discharging (dc output low, external discharge fet off) regardless of cell or pack conditions. writing a 1 to this bit enables discharging, subject to override by the presence of any protection conditions. the DS2720 automatically sets this bit to 1 when it transitions from sleep mode to active mode. the de bit is a volatile r/w bit, initialized to 1 upon por. status register the default values for the status register bits are stored in lockable eeprom in the corresponding bits of address 31h. a recall data command fo r eeprom block 1 recalls the default values into the status register bits. the format of the status register is s hown in figure 5. the function of each bit is described in detail in the following paragraphs. figure 5. status register format address 01 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x x 0 rnaop 0 x x x
DS2720 10 of 21 bit 5? this bit is read only. the value of this bit is set by bit 5 of address 31h and is factory set to 0. the value of address 31h b it 5 must not be changed. rnaop ?read net address opcode. a value of 0 in this bit sets the opcode for the read net address command to 33h, while a 1 sets the opcode to 39h. this b it is read-only. the desired default value should be set in bit 4 of address 31h. th e factory default for rnaop is 0. bit 3? this bit is read only. the value of this bit is set by bit 3 of address 31h and is factory set to 0. the value of address 31h b it 3 must not be changed. x ?reserved bits. eeprom register the format of the eeprom register is shown in figur e 6. the function of each b it is described in detail in the following paragraphs. figure 6. eeprom register format address 07 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 eec lock x x x x bl1 bl0 eec ?eeprom copy flag. a 1 in this read-only bit indicates that a copy data command is in progress. while this bit is high, writes to eeprom addresses are ignored. a 0 in this bit indicates that data can be written to unlocked eeprom bloc ks if the DS2720 is in the active mode of operation. lock ?eeprom lock enable. when this bit is 0, the lock command is ignored. writing a 1 to this bit enables the lock command. after the lock command is executed, the lock bit is reset to 0. the lock bit is a volatile r/w bit, initialized to 0 upon por. bl1? eeprom block 1 lock flag. a 1 in this read-onl y bit indicates that eeprom block 1 (addresses 30 to 33h) is locked (read-only) while a 0 indicates block 1 is unlocked (read/write). bl0? eeprom block 0 lock flag. a 1 in this read-onl y bit indicates that eeprom block 0 (addresses 20 to 23h) is locked (read-only) while a 0 indicates block 0 is unlocked (read/write). x ?reserved bits.
DS2720 11 of 21 special feature register the format of the special feature register is shown in figure 7. the function of each bit is described in detail in the following paragraphs. figure 7. special feature register format address 08 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 psf x x x x x x ot psf? ps flag. this bit is reset to 0 when the DS2720 detects the ps pin is pulled to v ss . this bit does not set itself to a 1 after the ps pin returns to a high logic level, and thus must be set by the host system to detect future events. this bit is initialized to a 1 upon por. ot ?overtemperature flag. when set to 1, this bit indicates the battery pack has experienced an overtemperature condition. this bit does not clear itself after the overtemperature state is corrected, and thus must be reset by the host system after the temperature decreases below t max to re-enable the charge and discharge fets. writing a 1 to this bit disables the fets, but this is not recommended. the ot bit is a volatile r/w bit, initialized to 0 upon por. x ?reserved bits. ps input pin the ps pin is internally pulled to v dd through a high-value resistance. ps is continuously monitored for a low-impedance connection to v ss . connecting ps to v ss wakes up the DS2720 if it was in sleep mode. if the DS2720 was in active mode, ps has no effect. 1-wire bus system the 1-wire bus is a system that has a single bus master and one or more slaves. a multidrop bus is a 1- wire bus with multiple slaves. a single-drop bus has only one slave device. in all instances, the DS2720 is a slave device. the bus master is typically a mi croprocessor in the host system. the discussion of this bus system consists of four topics : 64-bit net address, hardware config uration, transaction sequence, and 1-wire signaling. 64-bit net address each DS2720 has a unique, factory-programmed 1-wire ne t address that is 64 bits in length. the first eight bits are the 1-wire family code (31h for DS2720) . the next 48 bits are a unique serial number. the last eight bits are a crc of the first 56 bits (see figure 8). the 64-bit net address and the 1-wire i/o circuitry built into the device enable the DS2720 to communicate through the 1-wire protocol detailed in the 1-wire bus system section of this data sheet.
DS2720 12 of 21 figure 8. 1-wire net address format 8-bit crc 48-bit serial number 8-bit family code (31h) msb lsb crc generation the DS2720 has an 8-bit cyclic redundancy check (crc) st ored in the most significant byte of its 1-wire net address. to ensure error-free transmission of th e address, the host system can compute a crc value from the first 56 bits of the address and compare it to the crc from the DS2720. the host system is responsible for verifying the crc value and taking action as a result. the DS2720 does not compare crc values and does not prevent a command sequence from proceeding as a result of a crc mismatch. proper use of the crc can result in a communication channel with a very high level of integrity. the crc can be generated by the host using a circuit consisting of a shift register and xor gates as shown in figure 9, or it can be generated in software. additional information about the dallas 1-wire crc is available in application note 27, understanding and using cyclic redundancy checks with dallas semiconductor t ouch memory products . in the circuit in figure 9, the shift register bits are initialized to 0. then, starting with the least significant bit of the family code, one bit at a time is shifted in. after the 8th bit of the family code has been entered, then the serial number is entered. after the 48th b it of the serial number has been entered, the shift register contains the crc value. figure 9. 1-wire crc generation block diagram hardware configuration because the 1-wire bus has only a single line, it is important that each device on the bus be able to drive it at the appropriate time. to facilitate this, each devi ce attached to the 1-wire bus must connect to the bus with open-drain or tri-state output drivers. the ds 2720 uses an open-drain output driver as part of the bidirectional interface circuitry show n in figure 10. if a bidirecti onal pin is not available on the bus master, separate output and input pins can be connected together. the 1-wire bus must have a pullup resistor at the bus-master end of the bus. for short line lengths, the value of this resistor should be approximately 5k . the idle state for the 1-wire bus is high. if, for any reason, a bus transaction must be suspended, the bus mu st be left in the idle state in order to properly resume the transaction later. if the bus is left low for more than 120 s, slave devices on the bus begin to interpret the low period as a reset pulse, effectively terminating the transaction. msb xor xor lsb xor input
DS2720 13 of 21 figure 10. 1-wire bus interface circuitry transaction sequence the protocol for accessing the DS2720 thro ugh the 1-wire port is as follows: initialization net address command function command transaction/data the sections that follow describe each of these steps in detail. all transactions of the 1-wire bus begin with an initialization sequence consisting of a reset pulse transmitted by the bus master followed by a presence pulse simultaneously transmitted by the DS2720 and any other slaves on the bus. the presence pulse tells the bus master that one or more devices are on the bus and ready to operate. for more details, see the 1-wire signaling section. net address commands once the bus master has detected the presence of one or more slaves, it can issue one of the rom commands described in the following paragraphs. th e name of each net addr ess command is followed by the 8-bit opcode for that command in square brackets. figure 11 presents a transaction flowchart of the rom commands. read net address [33h or 39h]. this command allows the bus master to read the DS2720?s 1-wire net address. this command can only be used if there is a single slave on the bus. if more than one slave is present, a data collision occurs when all slaves try to transmit at the same time (open drain produces a wired-and result). the rnaop bit in the status register selects the opcode for this command, with rnaop = 0 indicating 33h a nd rnaop = 1 indicating 39h. match net address [55h]. this command allows the bus master to specifically address one DS2720 on the 1-wire bus. only the addressed DS2720 responds to any subsequent func tion command. all other slave devices ignore the function command and wait fo r a reset pulse. this command can be used with one or more slave devices on the bus. 0.5 a (typ) 100 mosfet tx rx rx tx rx = receive tx = transmit +v pullup (2.0v to 5.5v) 4.7k bus master DS2720 1-wire port
DS2720 14 of 21 skip net address [cch]. this command saves time when there is only one 1-wire device on the bus by allowing the bus master to issue a function command w ithout specifying the address of the slave. if more than one slave device is present on the bus, a subsequent function command can cause a data collision when all slaves transmit data at the same time. search net address [f0h]. this command allows the bus master to use a process of elimination to identify the 1-wire net addresses of all slave devices on the bus. the search process involves the repetition of a simple three-step routine: read a bit, r ead the complement of the bit, then write the desired value of that bit. the bus master performs this simple three-step routine on each bit location of the net address. after one complete pass through all 64 bits, the bus master knows the address of one device. the remaining devices can then be identified on additional iterations of the process. see chapter 5 of the book of ds19xx ibutton ? standards for a comprehensive discussion of a net address search, including an actual example. resume command [a5h]. in a typical application the DS2720 can be accessed several times to complete control adjustment. to maximize data throughput in a multidrop environment, the resume command has been implemented. this function checks the st atus of an internal flag. if it is set, it directly transfers control in similar fashion to the skip net address command. the only way to set the internal flag is through successfully executing the match net address or search net address. once the flag has been set, the device can be repeatedly accessed through the resume command. accessing another device on the bus clears the flag, thus preventing two or more devi ces from simultaneously responding to the resume command function. function commands after successfully completing one of the net address commands, the bus master can access the features of the DS2720 with any of the function commands describe d in the following paragraphs. the name of each function is followed by the 8-bit opcode for that command in square brackets. the function commands are summarized in table 5. read data [69h, xx]. this command reads data from the DS2720 starting at memory address xx. the lsb of the data in address xx is available to be re ad immediately after the msb of the address has been entered. because the address is automatically incremented after the msb of each byte is received, the lsb of the data at address xx + 1 is available to be read immediately after the msb of the data at address xx. if the bus master continues to read beyond address ff h, data is read starting at memory address 00 and the address is automatically incremented until a reset pulse occurs. addresses labeled ?reserved? in the memory map contain undefined data. th e read data command can be termin ated by the bus master with a reset pulse at any bit boundary. write data [6ch, xx]. this command writes data to the DS2720 starting at memory address xx. the lsb of the data to be stored at address xx can be written immediately after the msb of address has been entered. because the address is automatically incremented after the msb of each byte is written, the lsb to be stored at address xx + 1 can be written immediately after the msb to be stored at address xx. if the bus master continues to write beyond address ffh, the data starting at address 00 is overwritten. writes to read-only addresses, re served addresses and locked eepro m blocks are ignored. incomplete bytes are not written. writes to unlocked eeprom blocks are to shadow ram rather than eeprom. see the memory section for more details. copy data [48h, xx]. this command copies the contents of shadow ram to eeprom for the 4-byte eeprom block containing address xx. copy data co mmands that address locked blocks are ignored. while the copy data command is executing, the eec bit in the eeprom register is set to 1 and writes to ibutton is a registered trademark of dallas semiconductor.
DS2720 15 of 21 eeprom addresses are ignored. reads and writes to non-eeprom addresses can still occur while the copy is in progress. the copy data command takes t eec time to execute, starting on the next falling edge after the address is transmitted. the copy data command is ignored by the DS2720 while in the sleep mode. recall data [b8h, xx]. this command recalls the contents of the 4-byte eeprom block containing address xx to shadow ram. lock [6ah, xx]. this command locks (write-protects) the 4-byte block of eeprom memory containing memory address xx. the lock bit in the eeprom register must be set to l before the lock command is executed. to help prevent unintentional locks, one must issue the lock command immediately after setting the lock bit (eeprom register, address 07h, bit 06) to a 1. if the lock bit is 0 or if setting the lock bit to 1 does not immediately precede the lock command, the lock command has no effect. the lock command is permanent; a locked block can never be written again. the lock command is ignored by the DS2720 while in the sleep mode. table 5. function commands command description command protocol bus state after command protocol bus data read data reads data from memory starting at address xx 69h, xx master rx up to 256 bytes of data write data writes data to memory starting at address xx 6ch, xx master tx up to 256 bytes of data copy data copies shadow ram data to eeprom block containing address xx 48h, xx master reset none recall data recalls eeprom block containing address xx to ram b8h, xx master reset none lock permanently locks the block of eeprom containing address xx 6ch, 07h, 4xh 6ah, xx master reset none
DS2720 16 of 21 figure 11. net address command flow chart master tx reset pulse DS2720 tx presence pulse master tx net address command 33h/39h read f0h search DS2720 tx family code 1 byte DS2720 tx serial number 6 bytes DS2720 tx crc 1 byte DS2720 tx bit 0 DS2720 tx bit 0 master tx bit 0 bit 0 match ? DS2720 tx bit 1 DS2720 tx bit 1 master tx bit 1 bit 1 match ? master tx function command DS2720 tx bit 63 DS2720 tx bit 63 master tx bit 63 no no yes yes no no yes yes 55h match master tx bit 0 bit 0 match ? master tx bit 1 bit 1 match ? master tx bit 63 bit 63 match ? no yes no no yes yes no yes clear resume flag set resume flag cch skip yes no a5h resume master tx function command yes no resume flag set? no yes clear resume flag clear resume flag
DS2720 17 of 21 i/o signaling the 1-wire bus requires strict signaling protocols to in sure data integrity. the f our protocols used by the DS2720 are the initialization sequence (reset pulse followed by presence pulse), write 0, write 1, and read data. all of these types of signaling except the presence pulse are initiated by the bus master. the initialization sequence required to begin any co mmunication with the DS2720 is shown in figure 12. a presence pulse following a reset pulse indicates the DS2720 is ready to accept a net address command. the bus master transmits (tx) a reset pulse for t rstl . the bus master then releases the line and goes into receive mode (rx). the 1-wire bus line is then pulled high by the pullup resistor. after detecting the rising edge on the dq pin, the DS2720 waits for t pdh and then transmits the presence pulse for t pdl . figure 12. 1-wire initialization sequence write-time slots a write-time slot is initiated when the bus master pulls the 1-wire bus from a logic-high (inactive) level to a logic-low level. there are two types of write-time slots: write 1 and write 0. all write-time slots must be t slot (60 s to 120 s) in duration with a 1 s minimum recovery time, t rec , between cycles. the DS2720 samples the 1-wire bus line between 15 s and 60 s after the line falls. if the line is high when sampled, a write 1 occurs. if the line is low when sampled, a write 0 occurs (see figure 13). for the bus master to generate a write 1 time slot, the bus line must be pulled low and then released, allowing the line to be pulled high within 15 s after the start of the write time slot. for the host to generate a write 0 time slot, the bus line must be pulled low and held low for the duration of the write-time slot. read-time slots a read-time slot is initiated when the bus master pulls the 1-wire bus line from a logic-high level to a logic-low level. the bus master must keep the bus line low for at least 1 s and then release it to allow the DS2720 to present valid data. the bus ma ster can then sample the data t rdv (15 s) from the start of the read-time slot. by the end of the read-time slot, the DS2720 releases the bus line and allows it to be pulled high by the external pullup resi stor. all read-time slots must be t slot (60 s to 120 s) in duration with a 1 s minimum recovery time, t rec , between cycles. see figure 13 for more information. t r s tl t pdl t r s th t pdh v dq v ss line type legend: bus master active low DS2720 active low resistor pullup both bus master and DS2720 active low dq
DS2720 18 of 21 figure 13. 1-wire write- and read-time slots v dq v ss t s l o t dq t l o w1 t s l o t write 0 slot write 1 slot t l o w 0 t re c >1 s DS2720 sample window min typ max 15 s 15 s 30 s DS2720 sample window min typ max 15 s 15 s 30 s line type legend: bus master active low DS2720 active low resistor pullup both bus master and DS2720 active low t s l o t read 0 slot read 1 slot t slot t rec >1 s t rdv master sample window master sample window t rdv v dq v ss dq
DS2720 19 of 21 absolute maximum ratings* voltage on pls, relative to v ss -0.3v to +18v voltage on cc, dc, and cp pins, relative to v ss -0.3v to +12v voltage on any other pin, relative to v ss -0.3v to +6v operating temperature range -40c to +85c storage temperature range -55c to +125c soldering temperature see ipc/jedec-std-020a * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (-20 c to +70 c, 2.5v v dd 5.5v) parameter symbol conditions min typ max units notes supply voltage v dd 2.5 5.5 v 1 data pin dq -0.3 5.5 v 1 dc electrical characteristics (-20 c to +70 c, 2.5v v dd 4.5v) parameter symbol conditions min typ max units notes dq = v dd 0 c t a 50 c 12.5 20 a 2 active current i active dq = v dd 25 a 2 sleep mode current i sleep dq = 0v, ps floating 1.5 2.5 a input logic high: dq v ih1 1.5 v 1 input logic high: ps v ih2 v dd - 0.2v v1, 6 input logic low: dq v il1 0.4 v 1 input logic low: ps v il2 0.2 v 1 output logic high: cc, dc v ohcp r load > 10m 8.5 9.0 9.5 v 1 output logic low: cc v olcc r load > 10m v dd v dd + 0.1 v1 output logic low: dc v oldc r load > 10m v pls 10v v pls v pls + 0.1 v1, 7 output logic low: dq v ol1 i ol = 4ma 0.4 v 1 dq input pulldown current i pd v dq = 0.4v 0.1 0.5 2.5 a ps pullup current i ps v ps = 0.4v 100 na cc pulldown resistance r ccpd 1.2 4 k dc pulldown resistance r dcpd 12 16 k
DS2720 20 of 21 electrical characteristics: protection circuitry (0 c to +50 c, 2.5v v dd 4.5v) parameter symbol min typ max units notes v ova 4.250 4.275 4.300 overvoltage detect v ovb 4.325 4.350 4.375 v 1, 3 v ovc 4.275 4.300 4.325 charge enable v ce typ - 75mv v ov /1.022 typ + 75mv v1, 3 undervoltage detect v uv typ - 120mv v ov /1.55 typ + 120mv v1, 3 overtemperature detect t max 70 90 110 c 3 overcurrent detect v oc 140 200 260 mv 1, 3 short-circuit detect v sc 2.0 2.3 2.6 v 1 overvoltage delay t ovd 0.75 1.0 1.25 s 3 undervoltage delay t uvd 90 125 160 ms 3 overcurrent delay t ocd 12 16 20 ms 3 short-circuit delay t scd 50 100 150 s test resistance, i tst active r tst1 311 k 5 test resistance, recovery charging r tst2 515 k 5 charger detect voltage v ch 20 60 120 mv electrical characteristics: 1-wire interface (-20 c to +70 c, 2.5v v dd 5.5v) parameter symbol min typ max units notes time slot t slot 60 120 s recovery time t rec 1 s write 0 low time t low0 60 120 s write 1 low time t low1 115 s read data valid t rdv 15 s reset time high t rsth 480 s reset time low t rstl 480 960 s presence detect high t pdh 15 60 s presence detect low t pdl 60 240 s active transition to cc/dc engage t on 100 ms 4 dq capacitance c dq 25 pf
DS2720 21 of 21 eeprom reliability specification: (-20 c to +70 c, 2.5v v dd 5.5v) parameter symbol min typ max units notes copy to eeprom time t eec 15ms eeprom copy endurance n eec 25,000 cycles eeprom data retention t eedr 4 years notes 1. all voltages are referenced to v ss . 2. specified with no resistive load on cc, dc, or cp. 3. contact the factory for different vo ltage trip points and delay periods. 4. typical load capacitance on cc, dc is 1000pf cp (charge pump reservoir cap) = 0.1 f. dc load total on cc, dc, cp > 10m . 5. r tst = |vpls - v dd | / i measured, with vpls = 3.2v, v dd = 3.6v when test current, i tst , active for r tst1 ; and vpls = 4.0v, v dd = 2.5v when recovery charging for r tst2 . 6. maximum high-to-low fall time is 5 s. 7. internal 10v clamp on dc pin limits dc output logic low when pls > 10v 8. short-circuit delay tested with v dd ramped from 3.1v to 1.9v in 5 s. delay measured from v dd = 2.5v to dc pin fall to 7v from v ohcp .

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